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EDA Technology and Application [Guan Ke, Liang Wenjia, Edited by Zhang Xiaobo] 2012 Edition

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  • Data size: 21.67 MB
  • Data language: Chinese version
  • Document format: PDF document
  • Data category: Electronic information
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EDA technology and application of: Off to eds Publication date: 2012
Series items: Brief introduction of electronic information planning textbooks for national colleges and universities "National electronic information planning textbooks for colleges and universities: EDA technology and application" is based on Altera's EPIC3 FPGA, and details the internal structure and functions of EPIC3 Design, Altera's FPGA design tool QuartusⅡ design method and VHDL hardware description language, and through corresponding example analysis, example design and expanded thinking training three links, guide the reader to quickly master FPGA design methods and design concepts, and through training Gradually improve your design level. At the end of each chapter, there are exercises to facilitate readers' learning and teaching. "National Electronic Information Planning Textbooks for General Colleges and Universities: EDA Technology and Application" can be used as textbooks and experiments for electronic design or EDA technology courses for undergraduates or graduate students in electronic engineering, communications, industrial automation, computer application technology and other disciplines The instruction book can also be used as a reference book for related professional and technical personnel.
Chapter 1 Introduction 1.1 Classification of pld 1.2 Basic flow of pld design 1.2.1 Design input 1.2.2 Design synthesis 1.2.3 Simulation verification 1.2.4 Design realization 1.2.5 Download verification 1.3 Common tools for pld design 1.3.1 altera Company design and development tools 1.3.2 Xilinx company design and development tools 1.4 pld technology development trend exercises Chapter 2 ep1c3 type fpga structure 2.1 logic array block 2.1.1 lab connection 2.1.2 lab control signal 2.2 logic unit 2.2.1 lut chain and register Chain 2.2.2 addnsub signal 2.2.3 le operation mode 2.3 multipath interconnection 2.3.1 row interconnection 2.3.2 column interconnection 2.4 embedded memory 2.4.1 memory mode 2.4.2 parity bit support 2.4.3 shift Register support 2.4.4 Memory size configuration 2.4.5 Byte enable 2.4.6 Control signals and m4k interface 2.4.7 Independent clock mode 2.4.8 Input / output clock mode 2.4.9 Read / write clock mode 2.4.10 Single port Mode 2.5 Global clock network and phase-locked loop 2.5.1 Global clock network 2.5.2 Dual-purpose clock pin 2.5.3 Combined resources 2.5.4 Phase-locked loop 2.5.5 Multiplication and division of clock 2.5.6 External clock input 2.5.7 External clock output 2.5.8 Clock feedback 2.5.9 Phase shift 2.5.10 Lock Fixed detection signal 2.5.11 programmable duty cycle 2.5.12 control signal 2.6 input / output structure 2.6.1 external ram interface 2.6.2 ddr sdram and fcram 2.6.3 programmable drive capability 2.6.4 programmable pull-up resistor 2.7 ieee standard 1149.1 (jtag) boundary scan support exercises Chapter 3 fpga design method based on quartus ii 3.1 quartus ii software design input 3.1.1 text editor 3.1.2 module and symbol editor 3.1.3 megawizard plug-in manager 3.1. 4 Other design inputs supported by quartus ii 3.2 Design constraints of quartus ii software 3.2.1 Assignment editor 3.2.2 Pin planner 3.2.3 settings dialog 3.2.4 Assign design partition 3.2.5 Import assignment 3.2.6 Verify Pin assignment 3.3 Design and synthesis of Quartus II software 3.3.1 Analysis & synthesis function option settings 3.3.2 View synthesis results 3.3.3 Progressive synthesis 3.4 Placement and routing 3.4.1 Placement and wiring settings 3.4.2 Viewing place and wiring results 3.4.3 Optimization Place and Route Results 3.5 Simulation 3.6 Timing Analysis 3.6.1 Use of Standard Timing Analyzer 3.6.2 TimeQuest Timing Analysis 3.7 Timing Approximation 3.7.1 Using Timing to Approximate the Planar Layout Figure 3.7.2 Using Timing Optimization Wizard 3.7.3 Use netlist optimization to achieve timing approximation 3.7.4 Use logiclock area to achieve timing approximation 3.7.5 Use design space manager to achieve timing approximation 3.7.6 Use progressive compilation to achieve timing approximation 3.8 Power analysis 3.8.1 Use powerplay function Power consumption analysis 3.8.2 Use powerplay early power estimator 3.9 Programming and configuration 3.9.1 Use of assembler 3.9.2 Use programmer to program one or more devices 3.10 Debug 3.10.1 signaltap ii logic analyzer 3.10.2 Use external logic analyzer 3.10.3 Use signalprobe 3.10.4 Use in system memory content editor Exercises Chapter 4 vhdl hardware description language 4.1 Digital circuit design method based on hardware description language 4.2 Overview of hardware design language

EDA技术与应用[关可,梁文家,张小博编著] 2012年版 Download address EDA technology and application [Guan Ke, Liang Wenjia, edited by Zhang Xiaobo] 2012 edition

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