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EDA Technology and Application Tutorial [Edited by Liu Yanping] 2012 Edition

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EDA technology and application of tutorials: Liu Yanping, GAO Zhen Bin Editor Published: 2012
Brief introduction "General Twelfth Five-Year Plan" teaching materials: EDA technology and application tutorial According to the requirements of engineering design, classroom teaching and experimental teaching, in order to improve the actual engineering design ability, a systematic and systematic study of EDA technology and related knowledge is made. A complete introduction; it focuses on the hardware description language (VHDL) and the method of designing digital logic circuits and digital systems with VHDL; this is a revolutionary change in the design method of electronic systems, and it must be mastered by electronic engineers in the 21st century Expertise. "Ordinary Advanced" Twelfth Five-Year Plan "Textbook: EDA Technology and Application Course" is divided into "Theoretical Chapter" and "Practical Chapter", a total of 9 chapters. The "Theory" details the basic knowledge of EDA technology, the structure principle of the target device, the design input method, the design optimization and logic synthesis of VHDL, the comprehensive development platform, and the typical application of EDA technology. Each chapter is equipped with exercises. "Practice" introduces the use of common EDA technology tools, experimental content and FPGA hardware system design. The content of the experiment includes three parts: basic experiment, comprehensive experiment and design experiment. Each experiment is followed by extended thinking questions, giving the learner enough space for thinking and creating. "General Twelfth Five-Year Plan" Textbook: EDA Technology and Application Tutorial can be used as a textbook for electronic design or EDA technology courses for undergraduates or graduate students in electronic engineering, communications, industrial automation, computer application technology and other disciplines in colleges and universities. The experimental instruction book can also be used as a reference book for related professional and technical personnel.
Chapter 1 Introduction
1.1 EDA Overview
1.1.1 Development History of EDA Technology
1.1.2 Basic Features of EDA Technology
1.1.3 EDA technology to achieve the goal
1.1.4 Hardware Description Language (HDL)
1.1.5 Basic tools of EDA technology
1.1.6 Basic Design Ideas of EDA Technology
1.1.7 EDA system-level design and development process
1.1.8 Development Trend of EDA Technology
1.2 Digital System Hardware Design Overview
1.2.1 Bottom-up design
1.2.2 Top-down design
1.2.3 Top-down technology design process and key technologies
1.2.4 Design Descriptive Style Exercises Chapter 2 Basic Elements and Basic Structure of VHDL Language Programs
2.1 VHDL language naming rules
2.1.1 Numeric text
2.1.2 String literals
2.1.3 Identifiers
2.1.4 Subscript name
2.1.5 Section name
2.1.6 Notes
2.2 VHDL data types and operators
2.2.1 Objects and Classification of VHDL Language
2.2.2 VHDL data types
2.2.3 VHDL language operator
2.3 The basic unit of VHDL language design and its composition
2.3.1 entity description
2.3.2 Construct
2.4 Several methods of VHDL construct description
2.4.1 Behavior description
2.4.2 Data flow description
2.4.3 Structure description
2.5 Package collections, libraries, and configurations
2.5.1 Libraries
2.5.2 Package Collection
2.5.3 CONFIGURATION
2.6 VHDL subroutine (SUBPROGRAM)
Chapter 3 Main Descriptive Statements of VHDL Language
3.1 Processing statements sequentially
3.1.1 WAIT statement
3.1.2 Assert Statement
3.1.3 Signal assignment statements
3.1.4 variable assignment statement
3.1.5 IF statement
3.1.6 CASE statement
3.1.7 LOOP statement
3.1.8 NEXT statement
3.1.9 EXIT statement
3.1.10 Procedure call statements
3.2 Concurrent processing statements
3.2.1 PROCESS statement
3.2.2 Concurrent Signal Assignment Statement
3.2.3 Conditional Signal Assignment Statement
3.2.4 Selective Signal Assignment Statement
3.2.5 Concurrent ProcedureCall Statement
3.2.6 BLOCK statement
3.2.7 component instantiation statements
3.2.8 Generate statements
3.3 Other statements and explanations
3.3.1 ATTRIBUTE description and definition statement
3.3.2 Text File Operations
4.1 Design of Combination Logic Circuit
4.1.1 Encoder, Decoder and Selector
4.1.2 Adder, Complementer
4.1.3 Tri-state gates and bus buffers
4.2 Sequential Circuit Design
4.2.1 Clock signal and reset signal
4.2.2 Trigger
4.2.3 Register
4.2.4 Counter
4.3 Memory
4.3.1 Some Common Problems in Memory Description
4.3.2 ROM (Read Only Memory)
4.3.3 RAM (Random Memory)
4.3.4 FIFO (First In, First Out)
4.4 Finite State Machine (FSM) Design
4.4.1 Design of general state machine
4.4.2 State value encoding
4.4.3 Residual state and fault tolerance technology
4.5 Design of Common Interface Circuits
4.5.1 Design of common display interface circuits
4.5.2 Common keyboard interface circuit design
4.5.3 Design of Common AD Conversion Interface Circuit
4.5.4 MCS-51 MCU and FPGA / CPLD Bus Interface Logic Design Exercises Chapter 5 System Design
5.1 Hierarchical design of the system
5.1.1 Introduction to System Hierarchical Design Ideas
5.1.2 Hierarchical Design of the System with VHDL
5.1.3 Using Graphic Input Method and VHDL Language Mixed Input to Realize the Hierarchical Design of the System
5.1.4 Application Examples of Hierarchical System Design
5.2 Application System Design Example
5.2.1 Multifunctional Digital Clock Design
5.2.2 Data Acquisition System Design
5.3 SOPC Technology Introduction
5.3.1 Introduction to SOPC
5.3.2 IP Module Exercises Chapter 6 Simulation and Implementation
6.1 Simulation
6.1.1 Simulation method
6.1.2 Design method of test (platform) program
6.1.3 Generation of simulation input information
6.1.4 Processing of simulation results
6.2 Logical Synthesis
6.2.1 Constraints
6.2.2 Craft Library
6.2.3 Basic steps of logic synthesis
6.3 Design and Implementation
6.3.1 Design and implement the carrier
6.3.2 Design implementation process
6.3.3 Relationship between Design Implementation and Logic Synthesis
6.4 Optimized Design
6.4.1 Algorithm Optimization
6.4.2 Code optimization
6.4.3 Optimization in the synthesis process
6.4.4 Other Design Skills Exercises Part 2 Chapter 7 Xilinx Software Basic Operations
7.1 Xilinx Software Process
7.1.1 Xilinx Software Introduction
7.1.2 Software Process
7.1.3 Schematic input method
7.2 Application of IP Core
7.3 Timing Constraints and Timing Analysis
7.3.1 Timing Analysis
7.3.2 Timing Constraints
7.3.3 Implementation of timing constraints
7.3.4 Timing Analysis Report Chapter 8 VHDL Design Experiment
8.1 Basic Application Experiment of Xilinx ISE14.1 Software
8.1.1 Basic Application of ISE Software
8.1.2 Experimental requirements
8.2 Basic experiments
8.2.1 Encoder
8.2.2 Seven-segment digital tube display decoding
8.2.3 Shift Register
8.2.4 Counter
8.2.5 Vending Machine
8.2.6 Traffic Light Controller
8.3 Comprehensive experiments
8.3.1 Multifunctional Digital Clock Experiment
8.3.2 Multiplier Experiment
8.4 Designed experiments
8.4.1 Design of Intellectual Competition Responder
8.4.2 Electronic Keyboard Design
8.4.3 Electronic Table Tennis Game System
8.4.4 Digital Password Lock Design
8.4.5 Data acquisition and detection system
8.4.6 Arbitrary Waveform Design
8.4.7 Digital Frequency Meter with Automatic Range Conversion
8.4.8 Elevator Automatic Controller
8.4.9 Comprehensive Experiment of 8 × 8 Dot Matrix Chinese Character Display
8.4.10 Design of FIR Filter Chapter 9 FPGA Hardware Circuit Design
9.1 FPGA hardware system composition
9.1.1 FPGA Hardware System
9.1.2 FPGA pins
9.2 Power circuit
9.2.1 FPGA Power Index Requirements
9.2.2 Power Solution
9.2.3 FPGA System Board Power Design Example
9.3 FPGA Configuration Circuit
9.3.1 Xilinx FPGA Configuration Overview
9.3.2 FPGA common configuration circuit
9.4 Memory Interface Circuit Design
9.4.1 High-speed SDRAM memory
9.4.2 Asynchronous SRAM (ASRAM) memory
9.4.3 Flash memory
9.4.4 DDR2 memory

EDA技术及应用教程[刘艳萍编] 2012年版 Download address EDA technology and application tutorial [edited by Liu Yanping] 2012 edition

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